LM98640CVAL datasheet(41/55 Pages) TI2

部品番号	LM98640CVAL

部品情報	LM98640QML-SP Radiation Hardness Assured (RHA), Dual Channel, 14-Bit, 40-MSPS Analog Front End With LVDS Output

PDF	55 Pages

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メーカー	TI2 [Texas Instruments]

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LM98640QML-SP

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SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

Product Folder Links: LM98640QML-SP

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Table 6. Register Definitions - Analog Configuration (continued)

ADDRESS

(BINARY)

TITLE

BASELINE

(BINARY)

BIT(s)

DESCRIPTION

00 0110

Sample & Hold

1000 0001

[7:0]

Sample & Hold Mode Register

[7]

Sample & Hold Mode Enable

0 Disabled.

1 Enabled.

[6:3]

Not Used.

[2:1]

Reference Buffer Power Level

11 100% Power. Used for FINCLK = 20-40MHz.

10 60% Power. Used for FINCLK = 10-20MHz.

01 60% Power. Used for FINCLK = 10-20MHz.

00 30% Power. Used for FINCLK = 5-10MHz.

[0]

Reserved.

00 0111

Status

0000 0000

[7:0]

Status Register. (Read Only)

[7:1]

Not Used.

[0]

False Lock Detect.

Indicates if DLL is locked into a half frequency state.

00 1001

Clock Monitor

0000 0000

[7:0]

Internal Clock Signal Monitor Register

[7:5]

Not Used.

[4:3]

Enable and select clocks to be monitored on the Digital Timing

Monitor. (DTM)

00 Disable Digital Timing Monitor Pins (DTM0, DTM1)

01 Send CLAMPEVEN to DTM0 pin, and SAMPLEEVEN to DTM1

10 Send CLAMPODD to DTM0 pin, and SAMPLEODD to DTM1

11 Send ODD tag and ADC Clock to the DTM.

[2:0]

Reserved. Set to 000.

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