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LAN9252/ML データシート(PDF) 230 Page - Microchip Technology

部品番号 LAN9252/ML
部品情報  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9252/ML データシート(HTML) 230 Page - Microchip Technology

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LAN9252
DS00001909A-page 230
 2015 Microchip Technology Inc.
12.14.8
ESC FEATURES SUPPORTED REGISTER
Offset:
0008h-0009h
Size:
16 bits
Bits
Description
ECAT
Type
PDI
Type
Default
15:12
RESERVED
RO
RO
0h
11
Fixed FMMU/SyncManager Configuration
0:
Variable configuration
1:
Fixed configuration
RO
RO
0b
10
EtherCAT Read/Write Command Support
0:
Supported
1:
Not supported
RO
RO
0b
9
EtherCAT LRW Command Support
0:
Supported
1:
Not supported
RO
RO
0b
8
Enhanced DC SYNC Activation
0:
Not available
1:
Available
Note:
This feature refers to the Activation Register and Acti-
vation Status Register
RO
RO
1b
7
Separate Handling of FCS Errors
0:
Not supported
1:
Supported, frame with wrong FCS and additional nibble will be
counted separately in Forwarded RX Counter
RO
RO
1b
6
Enhanced Link Detection MII
0:
Not available
1:
Available
RO
RO
1b
5
Enhanced Link Detection EBUS
0:
Not available
1:
Available
RO
RO
0b
4
Low Jitter EBUS
0:
Not available, standard jitter
1:
Available, jitter minimized
RO
RO
0b
3
Distributed Clocks (width)
0:
32-bit
1:
64-bit
RO
RO
1b
2
Distributed Clock
0:
Not available
1:
Available
RO
RO
1b
1
RESERVED
RO
RO
0b
0
FMMU Operation
0:
Bit oriented
1:
Byte oriented
RO
RO
0b



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