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LAN9252/ML データシート(PDF) 239 Page - Microchip Technology |
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LAN9252/ML データシート(HTML) 239 Page - Microchip Technology |
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239 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 239 LAN9252 12.14.20 AL CONTROL REGISTER Note 8: This register behaves like a mailbox if Device Emulation is off (Device Emulation bit of ESC Configuration Register is 0). The PDI must read this register after ECAT has written it. Otherwise, ECAT can not write again to this register. After rest, this register can be written by ECAT. Regarding mailbox functionality, both registers 0120h and 0121h are equivalent, e.g., reading 0121h is sufficient to make this register writable again. If Device Emulation is on, this register can always be written and it contents are copied to the AL Status Register. Reading this register from PDI clears all Event Requests (register 0220h bit 0). Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 0 PDI Operational/EEPROM Loaded Correctly 0: EEPROM not loaded, PDI not operational (no access to Pro- cess Data RAM) 1: EEPROM loaded correctly, PDI operational (access to Pro- cess Data RAM) RO RO 0b Note: Reading this register from ECAT clears the DL Status Event bit in the ECAT Event Request Register. For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0120h-0121h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:5 RESERVED Write as 0. R/W Note 8 R/WC 000h 4 Error Ind Ack 0: No Ack of Error Ind in AL status register 1: Ack of Error Ind in AL status register R/W Note 8 R/WC 0b 3:0 Initiate State Transition of Device State Machine 1h: Request Init State 2h: Request Pre-Operational State 3h: Request Bootstrap State 4h: Request Safe-Operational State 8h: Request Operational State R/W Note 8 R/WC 1h Bits Description ECAT Type PDI Type Default |
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