PCM3000ESLASH2K datasheet(22/44 Pages) TI2

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BCKIN

LRCIN

DIN

t(BCH)

t(BCL)

t(LRP)

t(LB)

t(BCY)

1.4 V

t(BL)

DOUT

t(BDO)

t(LDO)

0.5 VDD

t(DIS)

t(DIH)

1.4 V

T0021−02

SYSTEM CLOCK

PCM3000

PCM3001

SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004

BCKIN pulse cycle time

t(BCY)

300 ns (min)

BCKIN pulse duration, HIGH

t(BCH)

120 ns (min)

BCKIN pulse duration, LOW

t(BCL)

120 ns (min)

BCKIN rising edge to LRCIN edge

t(BL)

40 ns (min)

LRCIN edge to BCKIN rising edge

t(LB)

40 ns (min)

LRCIN pulse duration

t(LRP)

t(BCY) (min)

DIN setup time

t(DIS)

40 ns (min)

DIN hold time

t(DIH)

40 ns (min)

DOUT delay time to BCKIN falling edge

t(BDO)

40 ns (max)

DOUT delay time to LRCIN edge

t(LDO)

40 ns (max)

Rising time of all signals

t(RISE)

20 ns (max)

Falling time of all signals

t(FALL)

20 ns (max

Figure 22. Audio Data Input/Output Timing

The system clock for the PCM3000/3001 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling

frequency. The system clock can be either a crystal oscillator placed between XTI (pin 20) and XTO (pin 21), or

an external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (pin 22), and

XTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating.

When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected to

ground, the external clock must be tied to CLKIO. For best performance, the external-clock-input-2 circuit in

Figure 23 is recommended.

The PCM3000/3001 also has a system-clock detection circuit which automatically senses if the system clock is

operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided into

256 fS automatically. The 256-fS clock is used to operate the digital filters and the modulators.

Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 23 and

Figure 24 illustrate the typical system clock connections and external system clock timing.

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