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PCM3000

PCM3001

SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004

PDWN:

Bit 8 – ADC Power-Down Control

This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effect

on the DAC section or the contents of the mode registers.

PDWN

0

Power-down mode disabled (default)

1

Power-down mode enabled

BYPS:

Bit 7 – ADC High-Pass Filter Bypass Control

This bit enables or disables the high-pass filter for the ADC.

BYPS

0

High-pass filter enabled (default)

1

High-pass filter disabled (bypassed)

res:

Bit 6 – Reserved

This bit is reserved and should be set to 0.

ATC:

Bit 5 – DAC Attenuation Data Mode Control

When set to 1, the REGISTER 0 attenuation data is used for both DAC channels. In this case, the REGISTER 1

attenuation data is ignored.

ATC

0

Individual channel attenuation data control (default)

1

Common channel attenuation data control

IZD:

Bit 4 – DAC Infinite Zero Detection Circuit Control

This bit enables the infinite zero detection circuit in the PCM3000. When enabled, this circuit disconnects the

analog output amplifier from the delta-sigma DAC when the input is continuously zero for 65,536 consecutive

cycles of BCKIN.

IZD

0

Infinite zero detection disabled (default)

1

Infinite zero detection enabled

OUT:

Bit 3 – DAC Output Enable Control

When set to 1, the outputs are forced to VCC/2 (bipolar zero). In this case, all registers in the PCM3000 hold the

present data. Therefore, when set to 0, the outputs return to the previous programmed state.

OUT

0

DAC outputs enabled (default normal operation)

1

DAC outputs disabled (forced to BPZ)

DEM[1:0]:

Bits 2:1 – DAC De-Emphasis Control

These bits select the de-emphasis mode as shown.

DEM1

DEM0

0

0

De-emphasis OFF (default)

0

1

De-emphasis 48 kHz ON

1

0

De-emphasis 44.1 kHz ON

1

1

De-emphasis 32 kHz ON

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