| データシートサーチシステム |
|
74V1G07 データシート(PDF) 1 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
74V1G07 データシート(HTML) 1 Page - STMicroelectronics |
|
1 / 7 page ![]() 74V1G07 SINGLE BUFFER (OPEN DRAIN) PRELIMINARY DATA ® October 1999 s HIGH SPEED: tPD = 6.1 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =1 µA (MAX.) at TA =25 oC s HIGH NOISE IMMUNITY: VNIH =VNIL =28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUT s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V1G07 is an advanced high-speed CMOS SINGLE BUFFER (OPEN DRAIN) fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. The internal circuit is composed of 2 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V. PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODE: 74V1G07S 74V1G07C S (SOT23-5L) C (SC-70) 1/7 |
同様の部品番号 - 74V1G07 |
|
同様の説明 - 74V1G07 |
|
|
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |