ADC12DL080

SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013

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For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal

to the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM.

Single-Ended Operation

Performance with differential input signals is better than with single-ended signals. For this reason, single-ended

operation is not recommended. However, if single ended-operation is required and the resulting performance

degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the

driven input. The peak-to-peak input signal at the driven input pin should be twice the reference voltage to

maximize SNR and SINAD performance (Figure 41b). For example, set VREF to 1.0V, bias VIN− to 1.5V and drive

VIN+ with a signal range of 0.5V to 2.5V.

Because very large input signal swings can degrade distortion performance, better performance with a single-

ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and

Table 2 indicate the input to output relationship of the ADC12DL080.

Table 1. Input to Output Relationship – Differential Input

VIN+

VIN−

Binary Output

2’s Complement Output

VCM − VREF/2

VCM + VREF/2

0000 0000 0000

1000 0000 0000

VCM − VREF/4

VCM + VREF/4

0100 0000 0000

1100 0000 0000

VCM

VCM

1000 0000 0000

0000 0000 0000

VCM + VREF/4

VCM − VREF/4

1100 0000 0000

0100 0000 0000

VCM + VREF/2

VCM − VREF/2

1111 1111 1111

0111 1111 1111

Table 2. Input to Output Relationship – Single-Ended Input

VIN+

VIN−

Binary Output

2’s Complement Output

VCM − VREF

VCM

0000 0000 0000

1000 0000 0000

VCM − VREF/2

VCM

0100 0000 0000

1100 0000 0000

VCM

VCM

1000 0000 0000

0000 0000 0000

VCM + VREF/2

VCM

1100 0000 0000

0100 0000 0000

VCM + VREF

VCM

1111 1111 1111

0111 1111 1111

Driving the Analog Inputs

The VIN+ and the VIN− inputs of the ADC12DL080 consist of an analog switch followed by a switched-capacitor

amplifier. As the internal sampling switch opens and closes, current pulses occur at the analog input pins,

resulting in voltage spikes at the signal input pins. As the driving source attempts to counteract these voltage

spikes, it may add noise to the signal at the ADC analog input. To help isolate the pulses at the ADC input from

the amplifier output, use RCs at the inputs, as can be seen in Figure 43 and Figure 44. These components

should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the

system and this is the last opportunity to filter that input.

For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the

sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC

pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response. The

values of the RC shown in Figure 43 and Figure 44 are suitable for applications with input frequencies up to

approximately 70MHz.

Input Common Mode Voltage

The input common mode voltage, VCM, should be in the range of 1.0V to 2.0V and be a value such that the peak

excursions of the analog signal does not go more negative than ground or more positive than 2.6V. See

Reference Pins.

22

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