ADC12DL080

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SNAS345A – FEBRUARY 2006 – REVISED APRIL 2013

DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK, REFSEL/DCS, OF/DOEN, OEA/OF, OEB/DRDY. The

OEB/DRDY pin may also be configured as the DRDY output.

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 10 MHz to 80 MHz. The higher the input frequency, the more critical it is to have a low jitter

clock. The trace carrying the clock signal should be as short as possible and should not cross any other signal

line, analog or digital, not even at 90°.

The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the

charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This

is what limits the lowest sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Take care to

maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905 for

information on setting characteristic impedance.

It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is

used to drive other things, each driven pin should be a.c. terminated with a series RC to ground such that the

resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

(6)

where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of

"L" and tPD should be the same (inches or centimeters).

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12DL080 has a Duty Cycle Stabilizer which can be enabled using the

REFSEL/DCS pin. It is designed to maintain performance over a clock duty cycle range of 30% to 70% at 80

MSPS.

REFSEL/DCS

This pin is used in conjunction with VREF (pin 7) to select the reference source and turn the Duty Cycle Stabilizer

(DCS) on or off.

When REFSEL/DCS is LOW and VREF is HIGH, the internal 1.0V reference is selected and DCS is On.

When REFSEL/DCS is HIGH, an external reference voltage in the range of 0.8V to 1.2V should be applied to the

VREF input. DCS is On.

With this pin connected to VRMA or VRMB, DCS is Off.

When enabled, duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to

70% and generate a stable internal clock, improving the performance of the part.

Table 3. VREF, REFSEL/DCS Pin Functions

REFSEL/DCS (pin 11)

VREF (pin 7)

Reference

DCS

Logic LOW

Logic HIGH

Internal 1.0 V

ON

Logic High

0.8 to 1.2V

External

ON

VRMA or VRMB

Logic High

Internal 1.0V

OFF

VRMA or VRMB

0.8 to 1.2V

External

OFF

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