RF Signal

IN OUT

U1

GSM PA

VPC

Directional Coupler

C2

U2

Input

Coupled

Load

Output

C4

BIAS

VCC

GSM

ANTENNA

R5

RLOAD

R2

R3

C5

+

±

OUT

C3

R1

VCC

U3

V-

R4

SD

Shut Down

Ramp

Up/Down

V+

Schottky Diode

Detector

Copyright © 2016, Texas Instruments Incorporated

21

LMV712-N, LMV712-N-Q1

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SNOS534J – FEBRUARY 2001 – REVISED NOVEMBER 2016

Product Folder Links: LMV712-N LMV712-N-Q1

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Copyright © 2001–2016, Texas Instruments Incorporated

Typical Applications (continued)

8.2.2.2 Detailed Design Procedure

An AC voltage source applied to VIN charges capacitor C1 to the peak of the input. Diode D1 conducts positive

half cycles, charging C1 to the waveform peak. Including D1 inside the feedback loop of the amplifier removes

the voltage drop of D1 and allows an accurate peak detection of VIN on C1. When the input waveform falls below

the DC peak stored on C1, D1 is reverse biased. The low input bias current of A1 and the reverse biasing of D1

limits current leakage from C1. As a result, C1 retains the peak value even as the waveform drops to zero. A2

further isolates the peak value on C1 while completing the peak detector circuit by operating as a voltage

follower and reporting the peak voltage of C1 at its output.

R5 and C1 are properly selected so that the capacitor is charged rapidly to VIN. During the holding period, the

capacitor slowly discharge through C1, through leakage of the capacitor and the reverse-biased diode, or op amp

bias currents. In any cases the discharging time constant is much larger than the charge time constant. And the

capacitor can hold its voltage long enough to minimize the output ripple.

Resistors R2 and R3 limit the current into the inverting input of A1 and the noninverting input of A2 when power

is disconnected from the circuit. The discharging current from C1 during power off may damage the input circuitry

of the op amps.

The peak detector is reset by applying a positive pulse to the reset transistor. The charge on the capacitor is

dumped into ground, and the detector is ready for another cycle.

The maximum input voltage to this detector must be less than (V+ – VD), where VD is the forward voltage drop of

the diode. Otherwise, the input voltage must be scaled down before applying to the circuit.

8.2.3 GSM Power Amplifier Control Loop

Figure 37. GSM Power Amplifier Control Loop Schematic

8.2.3.1 Design Requirements

The control loop in Figure 37 controls the output power level of a GSM mobile phones. The control loop is used

to avoid intermodulation of base station receivers, to prevent intermodulation with other mobile phones, and to

minimize power consumption depending on the distance between mobile and base station.