STMPE1601 datasheet(24/58 Pages) STMICROELECTRONICS

部品番号	STMPE1601

部品情報	16-bit enhanced port expander with keypad and PWM controller Xpander Logic

PDF	58 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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Interrupt system

STMPE1601

24/58

9.1.1

Interrupt latency

When the generation of interrupts by the GPIO as input is enabled, the latency (time taken

from actual transition at GPIO to time of INT pin assertion) is shown in the following table:

INT_CTRL

Interrupt control register

Address:

0x10, 0x11

Buffer:

R, R/W

Reset:

0x00

Description:

The interrupt control register is used to configure the interrupt controller. It has a

global enable interrupt mask bit that controls the interruption to the host.

Table 17.

Interrupt latency

State of operation

Interrupt latency

Hibernation

10 uS max

Sleep

5 uS max

Active

2 uS max

987654

3210

INT_CTRL_msb

INT_CTRL_lsb

Reserved

IC2

IC1

IC0

RRRRRRR

RRRRR

000000

0000

[15:3] RESERVED

[2] IC2

[1] IC1: Output Interrupt Type

‘0’ = Level interrupt

‘1’ = Edge interrupt

[0] IC0: Global Interrupt Mask bit

When this bit is written a ‘1’, it will allow interruption to the host. If it is written with a ‘0’, then, it

disables all interruption to the host. Writing to this bit does not affect the INT_EN_MASK value.

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