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STW4810CHDRLF データシート(PDF) 18 Page - STMicroelectronics

部品番号 STW4810CHDRLF
部品情報  Power management for multimedia processors
PDF  78 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STW4810CHDRLF データシート(HTML) 18 Page - STMicroelectronics

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Functional description
STw4810
18/78
4.2.2
POWER OFF / VDDOK
●
In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM
detected, or ‘it_twarn’ bit set to “1” (
Table 18), then multimedia processor is reset
(PORn low during a minimum time of 312.5 µs) and restarted with no time-out. (see
Figure 5). In case of VDDOK falling edge because PWREN balls equals “0”, there is no
reset (PORn still high).
●
In case of PON falling edge (STw4810 switched off from modem) multimedia processor
is also reset with no time-out. We consider that clean switch off between modem and
multimedia processor is done by software directly.
Figure 5.
VDDOK block diagram
4.2.3
Sleep mode
STw4810 goes into sleep mode by different ways.
Whether VCORE, VIO_VMEM and VAUX are programmed to sleep mode or not is indicated
in
Table 27.
Digital block
&
vcore_monitor
vio_monitor
&
VDDOK
it_twarn
Reg status
register reset after
read operation
or PON falling edge
or PORN_VBAT.
mask_twarn
VDDOK
PORn
312.5 µs
(10* 32 Khz)
Under voltage detection
Operating voltage threshold value reached
PWREN



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