STA339BW datasheet(77/78 Pages) STMICROELECTRONICS

77 / 78 page

DocID15251 Rev 8

77/78

STA339BW

Revision history

Table 87. Document revision history

Date

Revision

Changes

09-Dec-2008

Initial release

16-Feb-2009

Updated names/descriptions for pins 17-20 in Chapter 2 on page 12

Added cross reference to I2S interface setup in Section 3.6: Power

on/off sequence on page 18

Updated text and Figure 23: Application diagram on page 72

Updated Section 8.2: PLL filter on page 72

01-Apr-2009

Updated Y dimension in Table 86: PowerSSO-36 EPD dimensions

on page 75

15-May-2009

Updated Chapter 1 on page 10 to “8 programmable 28-bit biquads”

Updated Iil and Iih in Table 6: Electrical specifications - digital section

on page 15

Updated Ilim and Isc in Table 7: Electrical specifications - power

section on page 16

Updated register FDRC addresses in Section 7.1.5: Fault detect

recovery bypass on page 30

Updated bits 4 and 5 in Table 74: Status register bits on page 65.

04-Aug-2010

Updated order code in Table 1: Device summary on page 1

Updated name of Chapter 10 on page 75 to Package mechanical

data

18-Sep-2013

Added Section 4 on page 20

Modified Note:: The read write operation on RAM coefficients works

only if RLCKI (pin29) is switching and stable (ref. Table 9, tLRJT

timing) and PLL must be locked (ref bit D7 reg 0x2D). on page 60

Updated Company information appearing on last page of document

13-Feb-2014

Updated order code in Table 1 on page 1

05-Jan-2015

Updated Ilim in Table 7: Electrical specifications - power section

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