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L9907 データシート(PDF) 15 Page - STMicroelectronics

部品番号 L9907
部品情報  Automotive FET driver for 3 phase BLDC motor
PDF  49 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9907 データシート(HTML) 15 Page - STMicroelectronics

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L9907
Functional description
48
The gain of each CSA can be independently configured selecting between four different
values via dedicated bits in the SPI register CMD0; G10, G11 for CSA1 and G20, G21 for
CSA2.
Current Sense Amplifier is active if IC is active (VCC and VDD present and within spec
range), despite the EN status. In case Boost converter is disabled, but voltage at BST_C pin
is present, Current Sense Amplifiers work but with degraded performances at least in
common mode dynamic range.
2.7
System clock
2.8
General SPI usage
For device programmability a four-wire SPI is used. The device acts as SPI slave. Data will
be latched on the negative clock edge and shifted out on the positive edge (µC setting:
CPHA =1; CPOL = 0).
To perform an SPI write the WE bit has to be set and a correct ODD parity bit has to be
written.
A data read out is always performed on the following SPI frame (after power-up CMD0 is
read). That means sending data to a certain register will lead to shift out the content of the
addressed register in the following SPI frame. In case of wrong SPI communication (e.g.
due to stuck at 0 or at 1 of SDI) the current command is rejected and an error message
(0xB001) is presented as SDO response at the following SPI cycle.
Table 3. Offset bit configuration
Offx
SOFS1
SOFS2
Output Offset
0
Open
Closed
20% VCC
1
Closed
Open
50% VCC
Table 4. Gain bit configuration
Gx1
Gx0
SG1
SG2
SG3
SG4
Gain
0
0
Closed
Open
Open
Open
10
0
1
Closed
Closed
Open
Open
30
1
0
Open
Open
Closed
Open
50
1
1
Open
Open
Open
Closed
100
Table 5. System clock frequency
Symbol
Parameter
Min
Typ
Max
Unit
CLK_freq
System Clock Frequency
-
5.6
-
MHz



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