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L9907TR データシート(PDF) 29 Page - STMicroelectronics

部品番号 L9907TR
部品情報  Automotive FET driver for 3 phase BLDC motor
PDF  49 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L9907TR データシート(HTML) 29 Page - STMicroelectronics

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L9907
SPI operation
48
4
SPI operation
The L9907 SPI is a standard 16-bit, four wire interface. By means of the SPI most device
parameters can be internally set and the fault diagnostic can be read.
The timing diagram for the SPI operation is reported in Figure 7 below. The IC reads the
input data at SDI pin on the falling edge of the SPI clock (SCK). The IC outputs the SPI data
at SDO pin on the rising edge of the SPI clock (SCK).
Figure 7. Timing diagram for the SPI operation.
The SPI protocol integrates an internal check to add robustness to the communication: a
writing attempt of a not allowed register, an incorrect parity frame or a wrong number of bits
(different than 16) results in a "SPI error bit", that is available at SDO immediately after
asserting CS the next time and before starting the SCK toggling.
If the current SPI cycle is affected by a communication error, the current SDI command is
rejected and a SPI error message (0xB001) is presented as SDO response at the following
SPI cycle.
CS
SCK
SDO
SPI error
Bi t ( 15) MS B
Bi t(14:1)
Bit(0)
LSB
SDI
MSB IN
Bi t(14:1)
LSB I N
1
1a
1b
2
3
4
5
6
7
8
9
10
11
CS
SCK
SDO
SPI error
Bi t ( 15) MS B
Bi t(14:1)
Bit(0)
LSB
SDI
MSB IN
Bi t(14:1)
LSB I N
1
1a
1b
2
3
4
5
6
7
8
9
10
11
GAPGPS00838
Table 22. SPI timing specifications
#
Parameter
Condition
Min.
Typ.
Max.
Unit
1
SCK Frequency (fSCK)1
-
-
8
MHz
2
SCK High/low time (tSCK-high, t-SCK-low)
1a, 1b
60
-
-
ns
3
Enable lead time (tlead)2
740
-
-
ns
4
Enable lag time (tlag)3
200
-
-
ns
5
Data valid time (tvalid)
4
Cload<60pF
@ fSCK=8MHz
--
50
ns
6
Data set up time (tSI-set)
Data hold time (tSI-hold)
5
6
30
30
--
ns
7
Disable time (tdisable)
7
120
ns
8
SCK, SI rise/fall time (trise, tfall)-
-
5
-
ns



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