L9907TR datasheet(38/49 Pages) STMICROELECTRONICS

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SPI operation

L9907

38/49

DS11800 Rev 5

Effects described in the following sections take into account that the corresponding Fault

Enable bit is set to '1'.

TH_SD (B12). Thermal shutdown.

Once Thermal shutdown threshold temperature is reached, all the FET drivers are

disabled and a cumulative fault information is available at FS_FLAG pin and

through SPI reading cycle, together with FET status (enable/disable). After cooling

down the FET drivers are automatically re-enabled once the temperature

becomes lower than (Tot -Thys: see Table 11) and the information about FET status

(enable/disable) is available at SDO pin through an SPI reading cycle. After

cooling down the SPI diagnostic bit remains set, and the pin FS_FLAG remains

asserted low. A SPI diagnostic read cycle clears the THSD bit and deactivates

high the FS_FLAG pin.

The filter time applied to this fault works on both edges of the input signal.

VB_OV (B11) and VB_UV (B10). VB over-voltage and under-voltage

When the device is active and an under or over-voltage condition on VB line is

present for a time longer than Td_VB, the fault is detected and internally latched.

Upon detection of under or over-voltage of VB, the FET drivers and the BOOST

regulator are disabled, the proper SPI bit is set and the FS_FLAG is asserted low.

After removal of the fault condition (VB returns inside its normal range), the

BOOST is automatically re-enabled, the FET drivers instead are restarted by

cycling EN signal (internal AND of EN1 and EN2 pins) from high to low to high. A

SPI diagnostic read cycle clears the SPI diagnostic flag releases the FS_FLAG pin

to high.

The filter time applied to this fault works on both edges of the input signal.

Vcc_OV (B9) and Vcc_UV (B8). VCC over-voltage and under-voltage

When an over-voltage condition appears on the VCC line for a time longer than

Td_Vcc, the fault is detected and internally latched, the device is then disabled.

In case of detected under or over-voltage of VCC, the FET drivers and the BOOST

regulator are disabled, the proper SPI bit is set and the FS_FLAG is asserted low.

After removal of the fault condition (Vcc returns inside its normal range), the

BOOST is automatically re-enabled, the FET drivers are restarted by cycling EN

signal (internal AND of EN1 and EN2 pins) from high to low to high. A SPI

diagnostic read cycle clears the SPI diagnostic flag and releases the FS_FLAG

pin to high.

The filter time applied to this fault works on both edges of the input signal.

UV_HS (B7). High-side FET drivers supply under-voltage

The voltage difference between boost output pin and high-side Drain connection is

monitored and, if it falls down below VG_UV_HS threshold for a time longer than

tUV_UG, a high-side under-voltage fault is detected and internally latched. All the

FET drivers are disabled and fault information is available at FS_FLAG pin and at

SDO pin through an SPI reading cycle.

The fault flag for the high-side FET drivers supply under-voltage is related to a

BOOST regulator under - voltage.

In case of detected fault, the FET drivers are disabled, the proper SPI bit is set

and the FS_FLAG is asserted low. After removal of the fault condition, the FET

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