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L9908 データシート(PDF) 44 Page - STMicroelectronics |
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L9908 データシート(HTML) 44 Page - STMicroelectronics |
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44 / 152 page  Table 32. Digital input electrical characteristics (Control Loop Pins) Symbol Parameter Test Condition Min Typ Max Unit Notes DI_in_hl_th High input voltage range - 2.0 - VIO+0.3 V - DI_in_ll_th Low input voltage range - -0.3 - 0.65 V - DI_in_hys Input voltage hysteresis - 120 300 570 mV - SPI_DI_in_ipu Pull up current Pin = GND 15 40 65 μA Type C DI_in_ipd Pull down current Pin = VIO -65 -40 -15 μA Type A DI_in_rpd Pull down resistance - 50 135 220 kΩ Type B DI_in_cap Input capacitance - - - 10 pF Not subject to production test Note: All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. The state of the PWM control pins INHn/INLn is echoed into dedicated SPI readable bits: INHn_ECHO and INLn_ECHO [n = 1, 2, 3], within the register GEN_STATUS2. 5.8.3 Digital Output (DO) Digital output pins on L9908 are used to transfer an internal digital information to an external user whose domain is defined by the VIO voltage. Depending on the information carried these pins can be divided into three categories: Table 33. Digital output pins functional partitioning Pins Description SDO SPI Pin (SPI communication related pin) CSO3/PVF CSA phase 3 analog output/Phase voltage comparator output feedback FS_FLAG Fault Handling Pin (Fault flag output pin) The digital output pin interface is developed by an HV push-pull output stage supplied by VIO and a driving stage supplied by the internal V3V3_DIG reference. Table 34. Digital output electrical characteristics Symbol Parameter Test Condition Min Typ Max Unit DO_in_hl High output voltage Iload = 1 mA VIO-0.215 - VIO V DO_in_ll Low output voltage Iload = -1 mA 0 - 0.2 V T_do_rt Output rise time Cload = 120 pF From 10% to 70% - - 35 ns T_do_ft Output fall time Cload = 120 pF From 10% to 70% - - 35 ns Note: All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. 5.9 Internal clock Table 35. Internal clock electrical characteristics Symbol Parameter Test condition Min Typ Max Unit CLK_freq System Clock Frequency CLK_SSM_EN = 0 - 20 - MHz CLK_freq_acc System Clock Frequency Accuracy CLK_SSM_EN = 0 -5 - +5 % L9908 Functional description DS13546 - Rev 5 page 44/152 |
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