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STPM098C データシート(PDF) 74 Page - STMicroelectronics |
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STPM098C データシート(HTML) 74 Page - STMicroelectronics |
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74 / 110 page  Where: VID_DAC_out _lsb is the minimum voltage step [1.22 mV]. VOUT_OFFSET [5:0], VOUT_TRIM [5:0] are the dedicated PMBus™ configuration bits (2’s complement). The default value is VOUT_OFFSET = VOUT_TRIM = 0x00. This is intended especially for DDR memory applications where voltages required are higher than the standard VID. VOUT_OFFSET and VOUT_TRIM have the same offset effect on the setpoint; thus, the resulting offset is the sum of the two parameters. The margin mode voltage (VOUT_MARGIN_HIGH/LOW - VOUT_COMMAND) for the n-th loop can be adjusted with respect to programmed value through a dedicated PMBus™ register as follows: VIDLn=VOUTCOMMAND+VOUTMARGINHIGH=VOUTCOMMAND+VIDDACoutlsb ×VOUTMARGINHIGH5:0 (29) VIDLn=VOUTCOMMAND+VOUTMARGINLOW=VOUTCOMMAND+VIDDACoutlsb×VOUTMARGINLOW5:0 Where: VID_DAC_out _lsb is the minimum voltage step [1.22 mV]. VOUT_MARGIN_HIGH [5:0], VOUT_MARGIN_LOW [5:0] are the dedicated PMBus™ configuration bits (module). The default value is VOUT_MARGIN_HIGH = VOUT_MARGIN_LOW = 0x00. The reference voltage VID for the n-th loop can be safe-guarded against accidental excessive voltage programming on previous commands through a dedicated PMBus™ register as follows: VID_MAX=VID_MAX_lsb×VOUT_MAX5:0 (30) Where: VID_MAX_lsb is the minimum voltage step [50 mV]. VOUT_MAX [5:0] are the dedicated PMBus™ configuration bits. The default value is VOUT_MAX = 0x00. If VOUTCOMMAND+VOUTTRIM+VOUTOFFSET<VOUTMAX,then: VIDLn= VOUTCOMMAND+9 ×VOUT_COMMAND_lsb+ VOUTTRIM+VOUTOFFSET ×VID_DAC_out_lsb If VOUTCOMMAND+VOUTTRIM+VOUTOFFSET≥VOUTMAX,then: VIDLn= 25× VOUTMAX+1 −1 ×VIDDACoutlsb (31) At loop controller startup the VID_Ln reference is linearly increased by control logic from 0V to the programmed setpoint in order to develop a soft-start boot ramp on output voltage. The SS slew rate can be programmed through a dedicated PMBus™ register as follows: SSSR=SSSRlsb×SSSRnCFG3:0 Where: SS_SR _lsb is the minimum slew rate step [1 V/ms]. SS_SRn_CFG [3:0] are the dedicated PMBus™ configuration bits [1 V/ms ~ 10 V/ms]. The default value is SS_SRn_CFG = 0x5 (5 V/ms). To allow power state management at system level, STPM098C implements a procedure to runtime change the regulation setpoint (VID). As an accidental runtime NVM configuration change must be avoided, a dedicated PMBus™ unlock command key is made available. MFR_UNLOCK [7:0] = 0x55 LOCK can be achieved by writing MFR_UNLOCK ≠ 0x55 Note: The MFR_UNLOCK command is intended only to support dynamic setpoint variation and related diagnostics that need tuning. MFR_UNLOCK usages different from what specified are not recommended or guaranteed. The target setpoint for the VID transition is configured by programming the standard PMBus™ commands: • VOUT_COMMAND • VOUT_TRIM • VOUT_OFFSET To avoid diagnostic triggering during output voltage transition (ex. UV/OV) a monitoring threshold adjustment should be applied along with the target VID configuration. This operation is supposed to be carried out by application software: no automatic threshold changes or diagnosis masking is performed by STPM098C. STPM098C Functional description DS14440 - Rev 1 page 74/110 |
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