AX−SIP−SFEU, AX−SIP−SFEU−API

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BLOCK DIAGRAM

Figure 1. Functional Block Diagram of the AX−SIP−SFEU / AX−SIP−SFEU−API

RX/TX

Switch and

Antenna

Interface

Transmit

Communication

Controller

CPU

Program

Memory

(FLASH)

Sigfox identity (ID, PAC)

Sigfox compliant

RAM

Power Mode

ADC

GPIO

UART

RF Synthesis

DAC

AX−SIP−SFEU / AX−SIP−SFEU−API

Receive

ANT

UARTRX

UARTTX

GPIO[14:0]

Dedicated

Status

Outputs

RADIO_LED

CPU_LED

TX_LED

RX_LED

application

(AX−SFEU only)

Control