ISL91301AII-H-EV1Z datasheet(9/60 Pages) RENESAS

9 / 60 page

FN8966 Rev.4.01

Page 9 of 59

Feb 20, 2020

ISL91301A, ISL91301B

1. Overview

1.5

Pin Descriptions

Pin Location

Pin Name

Type

Description

PVIN_A

Input

Power supply for Power Stage A

A2, B2

PH_A

Output

Switching node for Power Stage A

A3, B3

PGND_A

Input

Ground connection for Power Stage A

A4, B4

PGND_B

Input

Ground connection for Power Stage A

A5, B5

PH_B

Output

Switching node for Power Stage B

PVIN_B

Input

Power supply for Power Stage B

GPIO0

Input/Output

I2C clock

WDOG_RST

Input

Digital input, resets bucks to default output voltage

Input

Master chip enable input, NMOS logic threshold

GPIO1

Input/Output

I2C data

INT

Output

Interrupt line

VIN_SEL

Input

For 2.8V~5.5V VIN range, 4A per phase IOUT capability: Tie to AVIN

For 2.5V ~ 5.5V VIN range, 3A per phase IOUT capability: Tie to GND

VOUT4

Input

Output voltage sense for Buck4

RTN4

Input

Remote ground sense for Buck4

GND

Input

Analog chip ground

RTN1

Input

Remote ground sense for Buck1

RTN3

Input

Remote ground sense for Buck3

VOUT3

Input

Output voltage sense for Buck3

VOUT2

Input

Output voltage sense for Buck2

RTN2

Input

Remote ground sense for Buck2

VOUT1

Input

Remote output voltage sense for Buck1

AVIN_FILT

Output

Filtered analog supply voltage, 2.5V to 5.5V (VIN_SEL tied to GND);

2.8V to 5.5V (VIN_SEL tied to AVIN)

Place a decoupling capacitor close to the IC

VIO

Input

Supply voltage for digital communications. Nominally connected to

1.8V supply, can be tied to AVIN.

MPIO0

Input/Output

SPI clock

MPIO1

Input/Output

SPI/I2C selector. Low = SPI, High = I2C. For more information, see

“Serial Communication Interface”.

MPIO2

Input/Output

SPI master out, slave in

AVIN

Input

Analog supply voltage, 2.5V to 5.5V (VIN_SEL tied to GND); 2.8V to

5.5V (VIN_SEL tied to AVIN)

F2, G2

PH_C

Output

Switching node for Power Stage C

F3, G3

PGND_C

Input

Ground connection for Power Stage C

F4, G4

PGND_D

Input

Ground connection for Power Stage D

F5, G5

PH_D

Output

Switching node for Power Stage D

MPIO3

Input/Output

SPI master in, slave out

PVIN_C

Input

Power supply connection for Power Stage C

PVIN_D

Input

Power supply connection for Power Stage D

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