AD4086BBCZ datasheet(39/91 Pages) AD

39 / 91 page

Data Sheet

AD4086

DIGITAL INTERFACE

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Rev. 0 | 39 of 91

Status Data Transmission

The Interface Status A register (see the Interface Status A Reg-

ister section, Address 0x11) and device status register (see the

Device Status Register section, Address 0x14) contain status data

pertaining to the communications interface and the device itself,

respectively. This data enables troubleshooting of device configura-

tion during development and also provides continuous coverage of

potential communication issues between the host and the interface

once deployed. The SPI controller can access the data through

regular register read operations. However, the AD4086 can be con-

figured to autonomously transmit status data through the SDO line

every time while the SPI controller is sending the SPI instruction

phase data over the SDI. This feature is controlled through the

SEND_STATUS bit in the Interface Configuration C register (see

the Interface Configuration C Register section, Address 0x10), and

it is disabled by default. To enable this bit, set SEND_STATUS = 1.

The status data that is sent is taken from the Interface Status A reg-

ister and from the device status register, but the content is different

depending on the setting of the SHORT_INSTRUCTION bit in the

Interface Configuration B register (see the Interface Configuration

B Register section. (Note that the length of the instruction phase

also depends on this setting). See Table 16 and Table 17 for a

description of the status data sent in each case, where the status

data is sent MSB first.

Table 16. Device Status Data Sent Through the SDO in Long Instruction Mode (SHORT_INSTRUCTION = 0)

Bit

Name

Description

Not applicable

Bit 15 is always 0.

Not applicable

Bit 14 is always 0.

FIFO_FULL

Device Status Register Bit 7: FIFO Full Status Flag.

0: FIFO Not Full.

1: FIFO Full.

FIFO_READ_DONE

Device Status Register Bit 6: FIFO Read Done Flag.

0: FIFO Read Not Done.

1: FIFO Read Done.

HI_STATUS

Device Status Register Bit 5: High Threshold Detection Status Flag.

0: High Threshold Event Not Detected.

1: High Threshold Event Detected.

LO_STATUS

Device Status Register Bit 4: Low Threshold Detection Status Flag.

0: Low Threshold Event Not Detected.

1: Low Threshold Event Detected.

ADC_CNV_ERR

Device Status Register Bit 2: ADC Conversion Error Flag.

0: ADC Conversion OK.

1: ADC Conversion Error. A. Conversion period is lower than minimum value for speed grade. B. DSP error.

ROM_CRC_ERR

Device Status Register Bit 1: Read Only Memory (ROM) CRC and/or Error Correction Code (ECC) Failure Flag.

0: ROM CRC Check OK.

1: ROM CRC and/or ECC Failure.

POR_ANA_FLAG

Device Status Register Bit 3: POR Analog Status. Allows user to detect when an analog POR event has occurred. An analog POR

is triggered at power-up or when the logic supply drops to less than some threshold value, when the ADC reference drops to less

than some threshold value, or when the user issues a software reset.

0: Analog POR Flag Cleared.

1: Analog POR Event Detected.

POR_FLAG

Device Status Register Bit 0: POR Status. Allows user to detect when a POR event has occurred. A POR is triggered at power-up

or when the logic supply drops to less than some threshold value or when the user issues a software reset.

0: POR Flag Cleared.

1: POR Event Detected.

NOT_READY_ERR

Interface Status A Register Bit 7: Device Not Ready for Transaction. This bit is set if the user attempts to execute an SPI

transaction before the completion of digital initialization.

CLOCK_COUNT_ERR

Interface Status A Register Bit 4: Clock Count Error. This bit is set when an incorrect number of clocks is detected in a transaction.

CRC_ERR

Interface Status A Register Bit 3: CRC Error. This bit is set when the SPI controller does not send a CRC value or when the CRC

value calculated by the device does not match the value received from the SPI controller.

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