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AD4086BBCZ データシート(PDF) 44 Page - Analog Devices

部品番号 AD4086BBCZ
部品情報  14-Bit, 40 MSPS, Low Noise, Low Power SAR ADC
PDF  91 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD4086BBCZ データシート(HTML) 44 Page - Analog Devices

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Data Sheet
AD4086
DIGITAL INTERFACE
analog.com
Rev. 0 | 44 of 91
Self Clock Mode
In LVDS data interface mode, it is possible to disable the DCO+
and DCO− echo clock output (see the Echo Clock Mode section)
by setting LVDS_SELF_CLK_MODE = 1 in the ADC Data Interface
Configuration B register (see the ADC Data Interface Configuration
B Register section, Address 0x16). This setting puts the device
in self clock mode disabling the DCO+ and DCO− output driver,
with the benefit of saving interface power as well as reducing the
number of LVDS pairs required to interface with the host controller.
In this mode, the DCO+ and DCO− pins can be left disconnected;
therefore, in single-lane configurations, a minimum of two LVDS
pairs (CLK+ and CLK−, DA+ and DA−) are required to connect to
each AD4086 instance. The interface connectivity can further be
simplified by sharing the interface clock (CLK+ and CLK−) between
multiple AD4086 instances.
Figure 71. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Self Clock Mode
Figure 72. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Self Clock Mode



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