LM3224MM-ADJ datasheet(3/18 Pages) NSC

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Block Diagram

20097603

General Description

The LM3224 utilizes a PWM control scheme to regulate the

output voltage over all load conditions. The operation can

best be understood referring to the block diagram and Figure

1 of the Operation section. At the start of each cycle, the

oscillator sets the driver logic and turns on the NMOS power

device conducting current through the inductor, cycle 1 of

Figure 1 (a). During this cycle, the voltage at the V

C pin

controls the peak inductor current. The V

C voltage will in-

crease with larger loads and decrease with smaller. This

voltage is compared with the summation of the SW voltage

and the ramp compensation. The ramp compensation is

used in PWM architectures to eliminate the sub-harmonic

oscillations that occur during duty cycles greater than 50%.

Once the summation of the ramp compensation and switch

voltage equals the V

C voltage, the PWM comparator resets

the driver logic turning off the NMOS power device. The

inductor current then flows through the schottky diode to the

load and output capacitor, cycle 2 of Figure 1 (b). The NMOS

power device is then set by the oscillator at the end of the

period and current flows through the NMOS power device

once again.

The LM3224 has dedicated protection circuitry running dur-

ing normal operation to protect the IC. The Thermal Shut-

down circuitry turns off the NMOS power device when the

die temperature reaches excessive levels. The UVP com-

parator protects the NMOS power device during supply

power startup and shutdown to prevent operation at voltages

less than the minimum input voltage. The OVP comparator is

used to prevent the output voltage from rising at no loads

allowing full PWM operation over all load conditions. The

LM3224 also features a shutdown mode decreasing the

supply current to 0.1µA (typ.).

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