7.3 Feature Description

7.3.1 Architecture

The TXB0604 device architecture (see Figure 7-1) does not require a direction-control signal to control the

direction of data flow from A to B or from B to A. In a DC state, the output drivers of the device maintain a high or

low, but are designed to be weak, so the output drivers can be overdriven by an external driver when data on the

bus flows the opposite direction.

The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns

on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly,

during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up

the high-to-low transition. The typical output impedance during output transition is approximately 28Ω at VCCO =

1.8V, approximately 22Ω at VCCO = 2.5V, and 21Ω at VCCO = 3.3V.

One Shot

One Shot

1 k

T1

T2

One Shot

One Shot

1 k

T3

T4

A

B

VCCA

VCCB

Figure 7-1. Architecture of TXB0604 Device I/O Cell

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TXB0604

SCES983A – OCTOBER 2025 – REVISED MARCH 2026

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