AT25DF256 datasheet(9/47 Pages) RENESAS

部品番号	AT25DF256

部品情報	256-Kbit, 1.65 V Minimum SPI Serial Flash Memory with Dual-Read Support

PDF	47 Pages

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メーカー	RENESAS [Renesas Technology Corp]

ホームページ	http://www.renesas.com

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9 / 47 page

DS-AT25DF256-035 Rev.G

Page 9

2024-01-08

AT25DF256 Datasheet

Block Diagram

Figure 4. AT25DF256 Block Diagram

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF256 can be erased in three levels of granularity,

including a full-chip erase. The size of the erase blocks is optimized for both code and data storage applications,

allowing both code and data segments to reside in their own erase regions. Figure 5 shows each erase level.

Figure 5. Memory Architecture Diagram

32 kB

4 kB

1-256 Byte

Block Erase

Page Program

(52h Command)

(20h Command)

(02h Command)

4 kB

007000h – 007FFFh

256 Bytes

007F00h – 007FFFh

4 kB

006000h – 006FFFh

256 Bytes

007E00h – 007EFFh

4 kB

005000h – 005FFFh

256 Bytes

007D00h – 007DFFh

4 kB

004000h – 004FFFh

4 kB

003000h – 003FFFh

4 kB

002000h – 002FFFh

256 Bytes

000200h – 0002FFh

4 kB

001000h – 001FFFh

256 Bytes

000100h – 0001FFh

4 kB

000000h – 000FFFh

256 Bytes

000000h – 0000FFh

Block Erase Detail

Page Program Detail

Page Address

Block Address

Range

32 kB

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