STA027 datasheet(18/44 Pages) STMICROELECTRONICS

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5 Register description

STA027

18/44

CD00066274

Default value at soft reset assume :

–

ofact == 256

–

external crystal provide a CRYCK running at 14.31818 MHz

5.2.9

PLL_AUDIO_XDIV_176 :

Address : 0xE4 (228)

Type : RW - DEC

Software Reset : 2

Description :

This register must contain a XDIV value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1, 2 & 3.

Default value at soft reset assume :

–

ofact == 256

–

external crystal provide a CRYCK running at 14.31818 MHz

5.2.10 PLL_AUDIO_MDIV_176 :

Address : 0xE5 (229)

Type : RW - DEC

Software Reset : 8

Description :

This register must contain a MDIV value that enables the audio PLL to generate a frequency of

ofact*176 kHz for the PCMCK.See table 1,2 & 3.

Default value at soft reset assume :

–

ofact == 256

–

external crystal provide a CRYCK running at 14.31818 MHz

5.3

PLL_SYSTEM_CONFIGURATION registers description

5.3.1

PLL_SYSTEM_PEL_50 :

Address : 0xE6 (230)

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