STA333W datasheet(29/42 Pages) STMICROELECTRONICS

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STA333W

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Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and outputs 50% of the duty cycle.

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

Auto EAPD on clock loss

When active will issue a power device power down signal (EAPD) on clock loss detection.

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output will begin a soft-mute. After the mute condition is reached, EAPD will be

asserted to power down the power-stage, then the master clock to all internal hardware

expect the I2C block will be gated. This places the IC in a very low power consumption state.

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled).

Table 35.

Binary output mode clock loss detection

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Table 36.

LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 37.

Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

Table 38.

Power down

Bit

R/W

RST

Name

Description

6R/W

1PWDN

0: IC power down low-power condition

1: IC normal operation

Table 39.

External amplifier power down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: external power stage power down active

1: normal operation

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