ST7FOXK2 datasheet(89/226 Pages) STMICROELECTRONICS

89 / 226 page

ST7FOXF1, ST7FOXK1, ST7FOXK2

On-chip peripherals

89/226

Figure 42.

ST7FOXK2 Block diagram of break function

Output compare mode

To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers.

When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and

DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is

generated if the CMPIE bit is set.

In Single Timer mode the output compare function is performed only on CNTR1. The

difference between both the modes is that, in Single Timer mode, CNTR1 can be compared

with any of the four DCR registers, and in Dual Timer mode, CNTR1 is compared with DCR0

or DCR1 and CNTR2 is compared with DCR2 or DCR3.

Note:

The output compare function is only available for DCRx values other than 0 (reset value).

Duty cycle registers are buffered internally. The CPU writes in Preload Duty Cycle registers

and these values are transferred in Active Duty Cycle registers after an overflow event if the

corresponding transfer bit (TRANx bit) is set. Output compare is done by comparing these

active DCRx values with the counters.

PWM0

PWM1

PWM2

PWM3

PWM0

PWM1

PWM2

PWM3

BREAKCR1 register

BREAK1 pin

(Inverters)

PWM0

PWM1

PWM2

PWM3

BP1EN

BA1

Level

Selection

BR1SEL

ENCNTR2 bit

BREN1 bit

PWM0/1 Break Enable

PWM2/3 Break Enable

OEx

BR1EDGE

Comparator1

BREAKCR2 register

SWBR1

SWBR2

BP2EN

BA2

BR2SEL BR2EDGE

BREAK2 pin

Comparator2

Level

Selection

BREN2 bit

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