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MSC8103/D データシート(PDF) 52 Page - Freescale Semiconductor, Inc

部品番号 MSC8103/D
部品情報  Network Digital Signal Processor
PDF  104 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MSC8103/D データシート(HTML) 52 Page - Freescale Semiconductor, Inc

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MSC8103 Network Digital Signal Processor, Rev. 11
2-12
Freescale Semiconductor
Physical and Electrical Specifications
Figure 2-7.
Host Reset Configuration Timing
PORESET
Internal
HRESET
Input
Output (I/O)
SRESET
Output (I/O)
HRESET/SRESET are
extended for 512/515 BUS
clocks, respectively, from PLL
and DLL lock
PLL locks after
800 SPLLMFCLKs and
DLL locks 3073 BUS clocks
after PLL is locked.
When DLL is disabled,
reset period is shortened
by DLL lock time.
RSTCONF, HPE
pins are sampled
HRM, BTM
Any time
Host programs
Word
MODCK_H bits
are ready for PLL.
MODCK[1–3] pins
are sampled.
PORESET
Reset Configuration
1
2
3
5
4
6
asserted for
min 16
CLKIN.
PLL locked
DLL locked



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