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MSC8103/D データシート(PDF) 58 Page - Freescale Semiconductor, Inc |
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MSC8103/D データシート(HTML) 58 Page - Freescale Semiconductor, Inc |
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58 / 104 page  MSC8103 Network Digital Signal Processor, Rev. 11 2-18 Freescale Semiconductor Physical and Electrical Specifications 2.6.5.2 DMA Data Transfers Table 2-18 describes the DMA signal timing. The DREQ signal is synchronized with the falling edge of DLLIN. DONE timing is relative to the rising edge of DLLIN. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-18. Figure 2-11 shows synchronous peripheral interaction. 2.6.6 HDI16 Signals Table 2-18. DMA Signals Number Characteristic Minimum Maximum Units 72 DREQ set-up time before DLLIN falling edge 6 — ns 73 DREQ hold time after DLLIN falling edge 0.5 — ns 74 DONE set-up time before DLLIN rising edge 9 — ns 75 DONE hold time after DLLIN rising edge 0.5 — ns 76 DACK/DRACK/DONE delay after DLLIN rising edge 0.5 9 ns Figure 2-11. DMA Signals Table 2-19. Host Interface (HDI16) Timing1, 2 Number Characteristics3 Expression Value Unit 44a Read data strobe minimum assertion width4 HACK read minimum assertion width (1.5 × TC) + 5.0 Note 11 ns 44b Read data strobe minimum deassertion width4 HACK read minimum deassertion width TC + 5.0 Note 11 ns 44c Read data strobe minimum deassertion width4 after “Last Data Register” reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK minimum deassertion width after “Last Data Register” reads5,6 (2.5 × TC) + 5.0 Note 11 ns 45 Write data strobe minimum assertion width8 HACK write minimum assertion width (1.5 × TC) + 5.0 Note 11 ns 46 Write data strobe minimum deassertion width8 HACK write minimum deassertion width after ICR, CVR and Data Register writes5 (2.5 × TC) + 5.0 Note 11 ns 47 Host data input minimum set-up time before write data strobe deassertion8 Host data input minimum set-up time before HACK write deassertion — 5.0 ns DLLIN DREQ DONE Input DACK/DONE/DRACK Outputs 73 72 74 75 76 |
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