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Table 2.37

SCI timing (2) (2 of 2)

Conditions: VCC = AVCC0 = 1.6 to 3.6 V

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple

SPI

Slave access time

2.7 V ≤ VCC ≤ 3.6 V

tSA

—

tPcyc

Figure 2.26 to

Figure 2.29

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Slave output release time

1.8 V ≤ VCC ≤ 3.6 V

tREL

—

tPcyc

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

SCKn

master select

output

SCKn

slave select input

Note:

n = 0, 1, 3 to 5, 9

Figure 2.25

SCI simple SPI mode clock timing

tDr, tDf

tSU

tOH

tOD

MSB IN

DATA

LSB IN

MSB IN

MSB OUT

DATA

LSB OUT

IDLE

MSB OUT

SCKn

CKPOL = 0

output

SCKn

CKPOL = 1

output

MISOn

input

MOSIn

output

Note:

n = 0, 1, 3 to 5, 9

Figure 2.26

SCI simple SPI mode timing (master, CKPH = 1)

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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