WM8959 datasheet(73/155 Pages) WOLFSON

73 / 155 page

Pre-Production

WM8959

PP, May 2008, Rev 3.1

GPIO CONTROL REGISTERS

Table 37 shows how the dual-function GPIO pins are configured to operate in their different modes.

Note that the order of precedence described earlier applies.

and GPIO functions. Register field GPIO1_ENA enables the GPIO functionality on GPIO1. Register

bit AIF_TRIS, when set, takes precedence over AIF_SEL and GPIO1 and tri-states all GPIO pins.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

AIF_SEL

Audio Interface Select

0 = Audio interface 1

1 = Audio interface 2 (GPIO3/BCLK2,

GPIO4/DACLRC2, GPIO5/DACDAT2)

GPIO1_ENA

GPIO1 Enable

0 = GPIO1 not enabled

1 = GPIO1 enabled

R9 (09h)

AIF_TRIS

Audio Interface and GPIO Tristate

0 = Audio interface and GPIO pins

operate normally

1 = Tristate all audio interface and GPIO

pins

Table 37 GPIO and GPI Pin Function Select

The GPIO pins and the GPIO Register behaviour are also controlled by the register fields described

in Table 38. Note the order of precedence described earlier applies.

Pull-up and pull-down resistors may be enabled on any of GPIO1, GPIO3, GPIO4 and GPIO5. If

enabled, these settings take precedence over all other GPIO selections for that pin. Note that, by

default, the pull-down resistors on GPIO3, GPIO4 and GPIO5 are enabled.

When the GPIO pins are used as inputs, de-bounce and interrupt masking may be controlled on all

GPIO pins (including GPI7 and GPI8) using GPIOn_DEB_ENA and GPIOn_IRQ_ENA bits as shown

in Table 39.

For each of GPIO1 and GPIO3 to GPIO5, the register field GPIOn_SEL is used to select the pin

functions of the individual GPIO pins as shown in Table 39. Note that this control has the lowest

precedence and is only effective when GPIOn_PU, GPIOn_PD, AIF_TRIS, AIFSEL and GPIO1_ENA

are set to allow GPIO functionality on that GPIO pin.

WM8959 データシート(PDF) 73 Page - Wolfson Microelectronics plc

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