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AT45DB021E データシート(PDF) 10 Page - Renesas Technology Corp |
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AT45DB021E データシート(HTML) 10 Page - Renesas Technology Corp |
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10 / 69 page ![]() DS-AT45DB021E-8789 Rev. N Page 10 3/24/26 © 2012-2026 Renesas Electronics AT45DB021E Datasheet 4. Memory Array To provide optimal flexibility, the AT45DB021E memory array is divided into three levels of granularity comprising of sectors, blocks, and pages. Figure 3 illustrates the breakdown of each level and details the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page level. Figure 3. Memory Architecture Diagram Sector 0a = 8 pages 2,048/2,112 bytes Sector 0b = 120 pages 30,720/31,680 bytes Block = 2,048/2,112 bytes 8 Pages Sector 0a Page = 256/264 bytes Page 0 Page 1 Page 6 Page 7 Page 8 Page 9 Page 1,022 Page 1,023 Page 14 Page 15 Page 16 Page 17 Page 18 Sector Architecture Block Architecture Page Architecture Block 0 Block 1 Block 14 Block 15 Block 16 Block 17 Block 126 Block 127 Block 30 Block 31 Block 112 Block 113 Sector 7 = 128 pages 32,768/33,792 bytes Block 2 Sector 1 = 128 pages 32,768/33,792 bytes Sector 6 = 128 pages 32,768/33,792 bytes |
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