9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

2

9DB433

MAY 25, 2018

Pin Configuration

SMBus Address Selection and Readback

PLL Operating Mode Readback Table

Power Groups

Tri-Level Input Logic Pins

VDDR 1

28 VDDA

SRC_IN 2

27 GNDA

SRC_IN# 3

26 IREF

GND 4

25 PD#

VDD 5

24 VDD

DIF_1 6

23 DIF_6

DIF_1# 7

22 DIF_6#

OE1# 8

21 OE6#

DIF_2 9

20 DIF_5

DIF_2# 10

19 DIF_5#

VDD 11

18 VDD

BYP#_HIBW_LOBW 12

17 SMB_ADR_tri

SMBCLK 13

16 VDD

SMBDAT 14

15 GND

Notes:

Highlighted Pins are the differences between 9DB403 and

9DB433.

Pin 12 and Pin 17 are latched on power up. Please make sure

that the power supply to the pullup/pulldown resistors ramps at

the same time as the main supply to the chip.

SMB_ADR_tri

Address

Low

DA/DB

Mid

DC/DD

High

D8/D9

BYP#_LOBW_HIBW

MODE

Byte0, bit 3 Byte 0 bit 1

Low

Bypass

0

0

Mid

PLL 100M Hi BW

1

0

High

PLL 100M Low BW

0

1

VDD

GND

1

4

SRC_IN/SRC_IN#

5,11,18, 24

4

DIF(1,2,5,6)

16

15

DIGITAL VDD/GND

28

27

Analog VDD/GND for PLL in IREF

For best results, treat pin 1 as analog VDD.

Description

Pin Number

State of Pin

Voltage

Low

<0.8V

Mid

1.2<Vin<1.8V

High

Vin > 2.0V