M51995AP/AFP

REJ03D0835-0201 Rev.2.01 Nov 14, 2007

Page 37 of 40

DET Circuit

Figure 41 shows how to use the DET circuit for the voltage detector and error amplifier.

C4

C2

R3

C1

C

F/B

DET

R1

Detecting

voltage

B

A

R2

M51995A

Figure 41 How to use the DET Circuit for the Voltage Detector

For the phase shift compensation, it is recommended to connected the CR network between DET terminal and F/B

terminal.

Figure 42 shows the gain-frequency characteristics between point B and point C shown in figure 41.

Log

ω

ω

1

ω

2

G1

GAVDET

(DC Voltage gain)

Figure 42 Gain-Frequency Characteristics between Point B and C shown in Figure 41

The G1,

ω

1 and ω2 are given by following equations;

G1 =

……………………… (12)

R3

R1 / R2

1

C2

• R3

ω1 =

………………………… (13)

C1 + C2

C1

• C2 • R3

ω2 =

………………… (14)

At the start of the operation, there happen to be no output pulse due to F/B terminal current through C1 and C2, as the

potential of F/B terminal rises sharply just after the start of the operation.

Not to lack the output pulse, is recommended to connect the capacitor C4 as shown by broken line.

Please take notice that the current flows through the R1 and R2 are superposed to ICC(START). Not to superpose, R1 is

connected to CVCC2 as shown in figure 25.