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PSD4235G2 データシート(PDF) 81 Page - STMicroelectronics

部品番号 PSD4235G2
部品情報  Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PDF  89 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD4235G2 データシート(HTML) 81 Page - STMicroelectronics

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PSD4235G2
Table 68. Port F Peripheral Data Mode Write Timing
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port F Data Peripheral mode.
4. Data is already stable on Port F.
5. Data stable on ADIO pins to data on Port F.
Figure 47. Peripheral I/O Write Timing
Symbol
Parameter
Conditions
-70
-90
Unit
Min
Max
Min
Max
tWLQV–PF
WR to Data Propagation Delay
(Note 2)
25
35
ns
tDVQV–PF
Data to Port F Data Propagation Delay
(Note 5)
22
30
ns
tWHQZ–PF
WR Invalid to Port F Tri-state
(Note 2)
20
25
ns
tDVQV (PF)
tWLQV
(PF)
tWHQZ (PF)
ADDRESS
DATA OUT
A / D BUS
WR
PORT F
DATA OUT
ALE /AS
AI05741



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