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RHF1401 データシート(PDF) 6 Page - STMicroelectronics |
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RHF1401 データシート(HTML) 6 Page - STMicroelectronics |
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6 / 29 page  Timing RHF1401 6/29 3 Timing Table 2. Timing characteristics Symbol Parameter Test conditions Min Typ Max Unit Fs Sampling frequency(1) 1. See clock recommendations in Section 7.2: Clock signal requirements on page 19 1.5 20 MHz Tck Sampling clock cycle(1) 50 667 ns DC Clock duty cycle Fs = 20 Msps 50 % TC1 Clock pulse width (high) 25 ns TC2 Clock pulse width (low) 25 ns Tod Data output delay (fall of clock to data valid) (2) 2. See Figure 3 and discussion below. 10 pF load capacitance 5 7.5 13 ns Tpd Data pipeline delay 8.5 8.5 8.5 cycles Tdr Data ready rising edge delay after data change 0.5 cycles Ton Falling edge of OEB to digital output valid data 1ns Toff Rising edge of OEB to digital output tri-state 1ns TrD Data rising time 10 pF load capacitance 6 ns TfD Data falling time 10 pF load capacitance 3 ns |
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