RHF1401

Application information

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7.2

Clock signal requirements

The signal applied to the CLK pin is critical to obtain full performance from the RHF1401. It

is recommended to use a 0V to 2.5V square signal with fast transition times, and to place

proper termination resistors as close as possible to the device.

It is the rising edge of the clock signal that determines the sampling instant. The jitter

associated with this instant must be as low as possible to avoid SNR degradation on fast

following condition for a full scale input signal:

For example, the total jitter with 14-bit resolution for a 10 MHz full scale input should be no

more than 1 picosecond (rms).

In most cases, it is the clock signal jitter that is the major contributor to the total jitter.

Therefore, you must pay particular attention to the clock signal in the case of acquisition of

fast signals with a low frequency clock. For further considerations on low sampling

conditions, refer to Section 7.4 on page 20.

The clock signal must be active when you power up the device. Clock gating (stopping the

clock) is not recommended due to possible undertermined states inside the circuit when the

clock is off.

7.3

Power consumption optimization

The internal architecture of the RHF1401 makes it possible for you to optimize the analog

This resistor is placed between the IPOL pin and the analog ground.

Input signal below 10MHz

(low sampling speed, low current) and 40 k

Ω (high sampling speed, high current). With a low

minimize the power consumption, often critical in space applications. This method is

efficient with an input signal in the range from DC up to 10MHz.

consumption.

Figure 23 shows the optimized power consumption of the circuit versus the sampling

frequency in two different configurations:

●

●

T

j

1

π F

in

2

n1

+

⋅⋅

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