 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
TDA7590 データシート(PDF) 22 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TDA7590 データシート(HTML) 22 Page - STMicroelectronics |
|
|
22 / 40 page  Appendix 1 TDA7590 22/40 ;;; Bit Definitions for M_TCS TUFCL EQU 16 ; Transmitter Data Overflow Clear TDE EQU 15 ; Transmitter Data Ready TUFL EQU 14 ; Transmitter Data Overflow ;Reserved TXIE EQU 12 ; Transmitter Interrupt Enable TDWE EQU 11 ; Transmitter Data Word Justification TREL EQU 10 ; Transmitter Relative Timing TCKP EQU 9 ; Transmitter Clock Polarity TLRS EQU 8 ; Transmitter Left Right Selection TDIR EQU 7 ; Transmitter Data Shift Direction TWL1 EQU 6 ; Transmitter Word Length Control 1 TWL0 EQU 5 ; Transmitter Word Length Control 0 ;Reserved TMME EQU 3 ; Transmitter Master Mode Enable T2EN EQU 2 ; Transmitter 2 enable T1EN EQU 1 ; Transmitter 1 enable T0EN EQU 0 ; Transmitter 0 enable ;------------------------------------------------------------------------ ; EQUATES for CODEC ;------------------------------------------------------------------------ CODEC_CSR EQU $FFFFCB ; CODEC Control Register Address ;;; Bit Definitions for CODEC GADCL_0 EQU 0 ; ADC Left Gain Bit 0 GADCL_1 EQU 1 ; ADC Left Gain Bit 1 GADCL_2 EQU 2 ; ADC Left Gain Bit 2 GADCR_0 EQU 3 ; ADC Right Gain Bit 0 GADCR_1 EQU 4 ; ADC Right Gain Bit 1 GADCR_2 EQU 5 ; ADC Right Gain Bit 2 GDACL_0 EQU 6 ; DAC Left Gain Bit 0 GDACL_1 EQU 7 ; DAC Left Gain Bit 1 GDACL_2 EQU 8 ; DAC Left Gain Bit 2 GDACR_0 EQU 9 ; DAC Right Gain Bit 0 GDACR_1 EQU 10 ; DAC Right Gain Bit 1 GDACR_2 EQU 11 ; DAC Right Gain Bit 2 MUTEDAC EQU 12 ; Mute DAC - Active Hi, Reset Val = 1 PDNDAC EQU 13 ; Power down DAC - Active Hi, Reset Val = 0 PDNADC EQU 14 ; Power down ADC - Active Hi, Reset Val = 0 N_RST EQU 15 ; Asynchronoue Reset - Active Lo, Reset Val = 1 ;------------------------------------------------------------------------ ; EQUATES for PLL ;------------------------------------------------------------------------ PLL_CSR EQU $FFFFD7 ; PLL Control/Status Register PLL_FCR EQU $FFFFD6 ; PLL Fractional Register PLL_CLKCTL EQU $FFFFD5 ; PLL Clock Control Register ;;; Bit Definitions for PLL_CSR IDF0 EQU 0 ; Input Divide Factor 0 IDF1 EQU 1 ; Input Divide Factor 1 IDF2 EQU 2 ; Input Divide Factor 2 IDF3 EQU 3 ; Input Divide Factor 3 IDF4 EQU 4 ; Input Divide Factor 4 ; Reserved |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
