TDA7590 datasheet(29/40 Pages) STMICROELECTRONICS

29 / 40 page

TDA7590

Appendix 1

29/40

INIT_TCPR2

EQU

$000000

;--- TPLR --------------------------------------------------------------------

; settings for the clock control register

;

321098765432109876543210

;INIT_TPLR

EQU

%001000000000001111100111

; $2003E7 source TIO0 / divider = 999+1

INIT_TPLR

EQU

%000000000000001111100111

; $0003E7 source internal / prescaler 999

;

x------------------------>

; Reserved. Write to zero for future compatibility.

;

01---------------------->

PS[1-0]

; Prescaler Source [00 internal / 01 external TIO0 /

;

external TIO0 / 11

external TIO0]

;

000000000010000000000->

PL[20-0] ; Prescaler Preload Value200400

;-------------------------------------------------------------------------------

;

Interrupt Initialisation Values

;-------------------------------------------------------------------------------

; settings for the Interrupt priority register - Core

;

321098765432109876543210

INIT_IPR_C

EQU

%000000000000000000000000

; $000000

; settings for the Interrupt priority register - peripherals

;

321098765432109876543210

INIT_IPR_P

EQU

%000000000011111001000100

; $29C4 glitch sull'uscita del dac

;

00---- HI

;

11------ ESSI0

;

00-------- ESSI1

;

11---------- SCI

;

11------------ TIMER

;

11 ------------- SAI

;

11 --------------- CODEC

;

00 ----------------- PLL

;

00 ------------------- Unknow

;

00 --------------------- I2C

;

00 ----------------------- SPI

;

00 ------------------------- EMI

;-------------------------------------------------------------------------------

;

Expansion Port Intitialisation values

;-------------------------------------------------------------------------------

;--- INIT_AAR0 -----------------------------------------------------------------------

; settings for the Address Attribute Register1

;

321098765432109876543210

INIT_AAR0

EQU

%110000000000010000010000 ; C00410

;

00 --- BAT

(00: Synchronous SRAM; 01: SRAM; 10: DRAM; 11: Reserved)

;

0 ----- BAAP (0:AA1 active low; 1: AA1 active high)

;

0 ------ BPEN (0: P space disabled; 1: P space enabled)

;

1 ------- BXEN (0: X data space disabled; 1: X data space enabled)

;

0 -------- BYEN (0: Y data space disabled; 1: Y data space enabled)

;

0 --------- BAM

(0: 8 LSB of address will appear on A0-A7;

;

1: 8 LSB of address will appear on A16-A23)

;

0 ---------- BPAC (0: packing disabled; 1: packing enabled)

;

0100 ----------- BNC

(Number of bits to compare; 1111, 1110, 1101 reserved)

;

110000000000 --------------- BAC

(Address to compare; BNC most significant)

;--- INIT_BCR -----------------------------------------------------------------------

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