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ST62T28C データシート(PDF) 29 Page - STMicroelectronics

部品番号 ST62T28C
部品情報  8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE
PDF  84 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST62T28C データシート(HTML) 29 Page - STMicroelectronics

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ST62T28C/E28C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused.
Bit 6 = LES:
Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB:
Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN:
Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on the ST62E28C/
T28C are summarized in the Table 10 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
Table 10. Interrupt Requests and Mask Bits
70
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
Mask bit
Masked Interrupt Source
Interrupt
source
GENERAL
IOR
C8h
GEN
All Interrupts, excluding NMI
All
TIMER
TSCR1
D4h
ETI
TMZ: TIMER Overflow
source 4
A/D CONVERTER
ADCR
D1h
EAI
EOC: End of Conversion
source 4
UART
UARTCR
D7h
RXIEN
TXIEN
RXRDY: Byte received
TXMT: Byte sent
source 4
ARTIMER
ARMC
E5h
OVIE
CPIE
EIE
OVF: ARTIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
source 3
SPI
SIDR
DCh
ALL
End of Transmission
source 1
Port PAn
ORPA-DRPA
C0h-C4h
ORPAn-DRPAn
PAn pin
source 1
Port PBn
ORPB-DRPB
C1h-C5h
ORPBn-DRPBn
PBn pin
source 2
Port PCn
ORPC-DRPC
C2h-C6h
ORPCn-DRPCn
PCn pin
source 0
Port PDn
ORPD-DRPD
C3h-C7h
ORPDn-DRPDn
PDn pin
source 2
29



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