ST63142 datasheet(23/86 Pages) STMICROELECTRONICS

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INTERRUPT (Continued)

VSYNC Interrupt (#2). The VSYNC Interrupt is

connected to the interrupt #2. When disabled the

VSYNC INT signal is low. Bit 5 of the interrupt op-

tion register C8h is used to select the negative

edge (ES2=0) or the positive edge (ES2=1); the

edge willdepend on the application. Note that once

an edge has been latched, then the only way to re-

move the latched signal is to service the interrupt.

Care must be taken not to generate spurious inter-

rupts. This interrupt may be used for synchronize

to the VSYNC signal in order to change characters

in the OSD only when the screen is on vertical

blanking (if desired). This method may also be

used to blink characters.

TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is

connected to the fourth interrupt #3 (0FF2h) which

detects a low level (latched in the timer).

TIMER 2 Interrupt (#4). The TIMER 2 Interrupt is

connected to the fifth interrupt #4 (0FF0h) which

detects a high to low level (latched in the timer).

Notes: Global disable does not reset edge sensi-

tive interrupt flags. These edge sensitive interrupts

become pending again when global disabling is re-

leased. Moreover, edge sensitive interrupts are

stored in the related flags also when interrupts are

globally disabled, unless each edge sensitive inter-

rupt is also individually disabled before the inter-

rupting event happens. Global disable is done by

clearing the GEN bit of Interrupt option register,

while any individual disable is done in the control

ripherals have an interrupt request flag bit (TMZ),

this bit is set to one when the device wants to gen-

erate an interrupt request and a mask bit (ETI) that

must be set to one to allow the transfer of the flag

bit to the Core.

ST63140,142,126,156

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