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ST7265X データシート(PDF) 75 Page - STMicroelectronics |
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ST7265X データシート(HTML) 75 Page - STMicroelectronics |
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75 / 166 page ![]() ST7265x 75/166 USB INTERFACE (Cont’d) Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the end- point status, as listed below: Table 21. Reception Status Encoding These bits are written by software. Hardware sets the STAT_RX and STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to ex- amine the received data before acknowledging a new transaction. Notes: If a SETUP is received while the status is other than DISABLED, it is acknowledged and the two directional status bits are set to NAK by hardware. When a STALL is answered by the USB device, the two directional status bits are set to STALL by hardware. ENDPOINT 1 RECEPTION REGISTER (EP1RXR) Read/Write Reset value: 0000 0000 (00h) This register is used for controlling Endpoint 1 re- ception. Bits 2:0 are also reset by a USB reset, ei- ther received from the USB or forced through the FRES bit in the CTLR register. Bits 7:4 Reserved, forced by hardware to 0. Bit 3 = CTR_RX Correct Reception Transfer. This bit is set by hardware when a correct transfer operation is performed in reception. This bit must be cleared after the corresponding interrupt has been serviced. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. The receiver toggles DTOG_RX only if it receives a correct data packet and the packet’s data PID matches the receiver sequence bit. Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the end- point status, as listed below: Table 22. Reception Status Encoding: These bits are written by software, but hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. STAT_RX1 STAT_RX0 Meaning 00 DISABLED: no function can be executed on this endpoint and messages related to this end- point are ignored. 01 STALL: the endpoint is stalled and all reception requests re- sult in a STALL handshake. 10 NAK: the endpoint is NAKed and all reception requests re- sult in a NAK handshake. 11 VALID: this endpoint is ena- bled (if an address match oc- curs, the USB interface handles the transaction). 70 0 000 CTR_R X DTOG _RX STAT_ RX1 STAT_ RX0 STAT_RX1 STAT_RX0 Meaning 00 DISABLED: reception trans- fers cannot be executed. 01 STALL: the endpoint is stalled and all reception requests re- sult in a STALL handshake. 10 NAK: the endpoint is naked and all reception requests re- sult in a NAK handshake. 11 VALID: this endpoint is ena- bled for reception. 1 |
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