| データシートサーチシステム |
|
ST72E121 データシート(PDF) 27 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72E121 データシート(HTML) 27 Page - STMicroelectronics |
|
27 / 92 page ![]() 27/92 ST72E121 ST72T121 I/O PORTS (Cont’d) Table 10. Port Configuration * Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value). Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must not be modified by the user otherwise a spurious interrupt may be generated. Port Pin name Input (DDR = 0) Output (DDR = 1) OR = 0 OR = 1 OR = 0 OR =1 Port A PA3 floating* pull-up with interrupt open-drain push-pull PA4:PA7 floating* true open drain, high sink capability Port B PB0:PB4 floating* pull-up with interrupt open-drain push-pull Port C PC0:PC7 floating* pull-up open-drain push-pull Port D PD0:PD5 floating* pull-up open-drain push-pull Port E PE0:PE1 floating* pull-up open-drain push-pull Port F PF0:PF2 floating* pull-up with interrupt open-drain push-pull PF4, PF6, PF7 floating* pull-up open-drain push-pull 27 |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |