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ST92F120JR9T データシート(PDF) 308 Page - STMicroelectronics |
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ST92F120JR9T データシート(HTML) 308 Page - STMicroelectronics |
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308 / 320 page  308/320 ST92F120 - ELECTRICAL CHARACTERISTICS SPI TIMING TABLE (VDD =5V ± 10%, TA = –40°C to +105°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified) Note: Measurement points are VOL,VOH,VIL and VIH in the SPI Timing Diagram. (1) Values guaranteed bu design. Legend: Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2 x OSCIN period when OSCIN is divided by 2; OSCIN period x PLL factor when the PLL is enabled. N ° Symbol Parameter Condition Value (1) Unit Min Max fSPI SPI frequency Master Slave fINTCLK / 128 0 fINTCLK /4 fINTCLK /2 MHz 1tSPI SPI clock period Master Slave 4 x Tck 2 x Tck ns 2tLead Enable lead time Slave 40 ns 3tLag Enable lag time Slave 40 ns 4tSPI_H Clock (SCK) high time Master Slave 80 90 ns 5tSPI_L Clock (SCK) low time Master Slave 80 90 ns 6tSU Data set-up time Master Slave 40 40 ns 7tH Data hold time (inputs) Master Slave 40 40 ns 8tA Access time (time to data active from high impedance state) Slave 0 120 ns 9tDis Disable time (hold time to high im- pedance state) 240 ns 10 tV Data valid Master (before capture edge) Slave (after enable edge) Tck / 4 120 ns ns 11 tHold Data hold time (outputs) Master (before capture edge) Slave (after enable edge) Tck / 4 0 ns ns 12 tRise Rise time (20% VDD to 70% VDD,CL = 200pF) Outputs: SCK,MOSI,MIS O Inputs: SCK,MOSI,MISO,SS 100 100 ns µs 13 tFall Fall time (70% VDD to 20% VDD,CL = 200pF) Outputs: SCK,MOSI,MIS O Inputs: SCK,MOSI,MISO,SS 100 100 ns µs 1 |
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