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STA014B データシート(PDF) 33 Page - STMicroelectronics

部品番号 STA014B
部品情報  MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM AND SRS WOWO POSTPROCESSING CAPABILITY
PDF  45 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA014B データシート(HTML) 33 Page - STMicroelectronics

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ADPCM_FRAME_SIZE
Address: 0xBD (189)
Type: R/W
Software Reset: 0x13
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
AFS7 AFS6 AFS5 AFS4 AFS3 AFS2 AFS1 AFS1
The ADPCM frame size may be adjusted to
match a trade-off between the bitrate overhead
and the frame length. The frame size (in bytes) is
calculated as follow:
FRAME size = (ADPCM_FRAME_SIZE * 90)
+108
The frame starts with a 12 bytes header:
- 6 bytes for DVI algorithm
- 96 bytes for G726 pack algorithms
ADPCM_INT_CFG
Address: 0xBE (190)
Type: R/W
Software Reset: 0x0B
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
INTL
6
INTL
5
INTL
4
INTL
3
INTL
2
INTL
1
INTL
0
X
Using this register the ADPCM interrupt capability
can be properly configured.
INTL0 -
INTL6
Interrupt Length
The interrupt length can be programmed,
using this bits, from 0 up to 128 system
clock cycles
GPIO_CONF
Address: 0xBF (191)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
XXXXXX
GOSP
GISP
This register controls how data are strobed on the
GPIO interface.
GISP:
GPIO Strobe Polarity in INPUT mode
0 =
data strobed an falling edge
1 =
data strobed on rising edge
GOSP:
GPIO Strobe Polarity in OUTPUT mode
0 =
non inverted
1 =
inverted
ADC_WLEN
Address: 0xC0 (192)
Type: R/W
Software Reset: 0x0F
Hardware Reset: 0x0F
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
AWL4 AWL3 AWL2 AWL1 AWL0
To select ADC word length AWL4 through AWL0
bits can be used. This 5 bit value must contain
the size of the significant data bits minus one.
ADC_WPOS
Address: 0xC1 (193)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
X
X
AWP4 AWP3 AWP2 AWP1 AWP0
These bits specify the position of the sample
word referred to the LRCK slot boundary. Bit
AWP0 thru AWP4 must be programmed with the
number of bits to ignore after the sample word.
STA014-STA014B-STA014T
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