ADE7569 datasheet(27/148 Pages) AD

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Preliminary Technical Data

ADE75xx/ADE71xx

Rev. PrE | Page 27 of 148

VSW.

Power supply monitor (PSM) interrupts can be enabled to

indicate when battery switchover occurs and when the VDD

power supply is restored - see the Power Supply Monitor

Interrupt (PSM) section.

Switching from VDD to VBAT

There are three events that can be enabled to switch the internal

power supply, VSW, from VDD to VBAT:

(VDCIN < 1.2 V):

When VDCIN falls below 1.2V VSW

switches from VDD to VBAT. This event is enabled when

the BATTPROG[1:0] bits in the Battery Switchover

Configuration SFR (BATPR, 0xF5) are clear. Setting

this bit will disable switchover based on VDCIN. Battery

switchover on low VDCIN is disabled by default.

(VDD < TBD V):

When VDD falls below TBD V VSW

switches from VDD to VBAT. This event is enabled when

BATTPROG[1] in the Battery Switchover

Configuration SFR (BATPR, 0xF5) is cleared.

Rising edge on BCTRL:

When the battery control

pin, BCTRL, goes high, VSW switches from VDD to VBAT.

This external switchover signal can trigger a

switchover to VBAT at any time. Setting bits

INT1PRG[4:2] to 0bx01 in the Interrupt pins

configuration SFR (INTPR, 0xFF) enables the battery

control pin.

Switching from VBAT to VDD

To switch VSW back from VBAT to VDD all of the events that are

enabled to force battery switchover must be false:

(VDCIN < 1.2 V) and (VDD < TBD V) Enabled:

If the

low VDCIN condition is enabled, VSW switches to VDD

after VDCIN remains above TBD V for TBD seconds

and VDD remains above TBD V for TBD seconds.

(VDD < TBD V) Enabled:

VSW switches back to VDD

after VDD has been above TBD V for TBD seconds.

BCTRL Enabled:

VSW switches back to VDD after

BCTRL is low and number 1 or number 2 are satisfied.

POWER SUPPLY MONITOR INTERRUPT (PSM)

The Power Supply Monitor Interrupt (PSM) alerts the 8052 core

of power supply events. The PSM interrupt is disabled by

default. Setting the EPSM bit in the Interrupt Enable and

Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt. The

Power Management Interrupt Enable SFR (IPSME, 0xEC)

controls the events that result in a PSM interrupt. Figure 10 is a

diagram illustrating how the PSM interrupt vector is shared

among the PSM interrupt sources. The PSM interrupt flags are

latched and must be cleared by writing to the flag register.

EPSR

ESAG

EBAT

EBSO

EVDCIN

FPSR

FSAG

FBAT

FBSO

FVDCIN

FPSM

IPSME Addr. 0ECh

IPSMF Addr. 0F8h

ETI

EPSM

ESI

PTI

PSI

IEIP2 Addr. 0A9h

ADEAUTOCLR

EPSR

ESAG

EBAT

EVSW

EBSO

FPSR

FSAG

FBAT

FVSW

FBSO

FPSM

Pending PSM interrupt

EPSM

TRUE?

EVSW

reserved

EADE

: Not involved in PSM Interrupt signal chain

FVSW

EVDCIN

FVDCIN

Figure 10: PSM Interrupt Sources

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