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STE2002DIE2 データシート(PDF) 10 Page - STMicroelectronics |
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STE2002DIE2 データシート(HTML) 10 Page - STMicroelectronics |
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10 / 51 page  STE2002 10/51 Figure 6. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)1 Figure 7. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)1 Figure 8. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)1 Figure 9. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)1 1. X Carriage=127; Y-Carriage = 12 0123 124 125 126 127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 0123 124 125 126 127 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 127 126 125 124 3 2 1 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 127 126 125 124 3 2 1 0 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 |
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