STLC5048 datasheet(6/45 Pages) STMICROELECTRONICS

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STLC5048

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No.

Name

Type

Description

CS0

DIO

Slic CS control #0. Depending on CONF reg. content can be a CS

output for SLIC #0 or a static I/O.

When configured as CS output it is automatically generated by the

CODEC with a repetition time of 31.25ms. In this mode also the

IO0..11 are synchronised and carry proper data in and out

synchronous with CS.

When configured as static I/O, the direction is defined by CSDIR

CS1

DIO

Slic CS control #1, (see CS0 description).

CS2

DIO

Slic CS control #2, (see CS0 description).

CS3

DIO

Slic CS control #3, (see CS0 description).

Chip Select Input, when this pin is low control information can be

written to or read from the device via the CI and CO pins.

CCLK

Clock of Serial Control Bus. This clock shifts serial control information

into or out of CI or CO when CS input is low depending on the current

instruction. CCLK may be asynchronous with the other system

clocks.

Control Data Input of Serial Control Bus.

Control data is shifted in the device when CS is low and clocked by

CCLK. Depending on the addressed register different numbers of

consecutive bytes can be loaded.

Control Data Output of Serial Control Bus.

Control data is shifted out the device when CS is low and clocked by

CCLK. Depending on the addressed register different numbers of

consecutive bytes can be shifted out.

INT

ODO

Interrupt output (open drain), goes low when a data change has been

detected in the I/O pins or another interrupt source is active. One

mask register allows to mask any I/O pin. Interrupt is reset when the I/

O register is read.

TSXB

ODO

Transmit Time Slot (open drain output, 3.2mA). Normally it is floating

in high impedance state except when a time slot is active on the DXB

output. In this case TSXB output pulls low to enable the backplane

line driver.

DXB

DTO

Transmit PCM interface B. It remains in high impedance state except

during the assigned time slots during which the PCM data byte is

shifted out on the rising edge of MCLK.

DRB

Receive PCM interface B. It remains inactive except during the

assigned receive time slots during which the PCM data byte is shifted

in on the falling edge of MCLK.

PIN DESCRIPTION (continued)

DIGITAL PIN DESCRIPTION (continued

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