STLS2F01 datasheet(22/48 Pages) STMICROELECTRONICS

部品番号	STLS2F01

部品情報	Loongson 2F: High performance 64-bit superscalar MIPS® microprocessor

PDF	48 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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DDR2 SDRAM controller interface description

STLS2F01

22/48

Figure 7.

DDR2 SDRAM read protocol

CAS latency = 3, read latency = 3, burst length = 8

4.3

DDR2 SDRAM write protocol

As showed in Figure 8 DDR2 SDRAM write protocol, the command (CMD) includes RAS_n,

CAS_n and WE_n. When a write request happens, RAS_n=1, CAS_n=0,and WE_n=0.

Unlike a read transaction, DQM is used to identify the write mask. In other words, the

number of written bytes is needed. DQM is synchronous with DQS.

Figure 8.

DDR2 SDRAM write protocol

CAS latency = 3, write latency = read latency = 2, burst length = 4

CMD

READ A

NOP

≤ tDQSCK

CL=3

RL=3

DOUTA1

DOUTA2

DOUTA3

DOUTA4

DOUTA5

DOUTA6

DOUTA7

CK/CK

DQS/DQS

DQS

CMD

WRITE A

NOP

Precharge

NOP

Bank A

Activate

≤ tDQS6

WL = RL - 1 = 2

DINA0

DINA1

DINA2

DINA3

CK/CK

DQS/DQS

DQS

≥ WR

≥ tRP

Completion of

the Burst Write

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