Device description and operation

PM8834

8/18

Figure 3.

Timing diagram

4.1.2

Enable pins

PM8834 features two independent enable signals, namely ENABLE_1 and ENABLE_2, to

control the operation of each low side driver. Both enable pins are internally pulled up to an

internal 3.3 V reference and are active high.

In noisy application where ENABLE_1 and ENABLE_2 are not in use, It is strongly

recommended to connect these pins to VCC directly or with a pull-up resistor.

ENABLE_1 and ENABLE_2 are compatible to CMOS/TTL levels and can be directly pulled

up to VCC.

By default, because of the internal pull-up, both drivers are enabled. It is possible to disable

one or both low side drivers connecting the corresponding enable signal to GND.

4.2

Output stage

The output stage of the PM8834 make use of ST proprietary lateral DMOS as depicted in

Figure 1. Both N-DMOS and P-DMOS have been sized to exhibit high driving peak current

as well as low ON-resistance: typical peak current is 4 A while output resistances are 1

Ω

and 0.7

Ω for P-DMOS and N-DMOS resistance respectively.

The device features adaptive anti cross-conduction protection. PM8834 continuously

monitors the status of the internal N-DMOS and P-DMOS: in case of a PWM transition,

before switching on the desired DMOS, the device waits until the other DMOS is completely

turned-off. No static current will then flow from VCC to GND.